721 lines
17 KiB
C
721 lines
17 KiB
C
/**
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* This file has no copyright assigned and is placed in the Public Domain.
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* This file is part of the w64 mingw-runtime package.
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* No warranty is given; refer to the file DISCLAIMER within this package.
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*/
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#define SHADOW_IRQL_IMPLEMENTATION 1
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#define PS0 0x0001
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#define PS1 0x0002
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#define PS2 0x0004
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#define PS3 0x0008
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#define PS4 0x0010
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#define PS5 0x0020
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#define PRP 0x0080
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#define PT0 0x0040
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#define PT1 0x0100
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#define PT2 0x0200
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#define PT3 0x0400
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#define PT4 0x0800
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#define PT5 0x1000
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#define PT6 0x2000
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#define PT7 0x4000
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#define PT8 0x8000
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#define NOM_BS0 0x0001
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#define NOM_BS1 0x0002
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#define NOM_BS2 0x0004
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#define NOM_BS3 0x0008
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#define NOM_BS4 0x0010
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#define NOM_BS5 0x0020
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#define NOM_BRP 0x0080
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#define NOM_BT0 0x0040
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#define NOM_BT1 0x0100
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#define NOM_BT2 0x0200
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#define NOM_BT3 0x0400
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#define NOM_BT4 0x0800
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#define NOM_BT5 0x1000
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#define NOM_BT6 0x2000
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#define NOM_BT7 0x4000
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#define NOM_BT8 0x8000
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#define PSR_MBZ4 0
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#define PSR_BE 1
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#define PSR_UP 2
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#define PSR_AC 3
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#define PSR_MFL 4
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#define PSR_MFH 5
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#define PSR_MBZ0 6
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#define PSR_MBZ0_V 0x7fi64
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#define PSR_IC 13
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#define PSR_I 14
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#define PSR_PK 15
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#define PSR_MBZ1 16
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#define PSR_MBZ1_V 0x1i64
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#define PSR_DT 17
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#define PSR_DFL 18
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#define PSR_DFH 19
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#define PSR_SP 20
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#define PSR_PP 21
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#define PSR_DI 22
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#define PSR_SI 23
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#define PSR_DB 24
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#define PSR_LP 25
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#define PSR_TB 26
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#define PSR_RT 27
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#define PSR_MBZ2 28
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#define PSR_MBZ2_V 0xfi64
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#define PSR_CPL 32
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#define PSR_CPL_LEN 2
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#define PSR_IS 34
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#define PSR_MC 35
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#define PSR_IT 36
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#define PSR_ID 37
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#define PSR_DA 38
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#define PSR_DD 39
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#define PSR_SS 40
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#define PSR_RI 41
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#define PSR_RI_LEN 2
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#define PSR_ED 43
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#define PSR_BN 44
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#define PSR_IA 45
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#define PSR_MBZ3 46
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#define PSR_MBZ3_V 0x3ffffi64
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#define PL_KERNEL 0
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#define PL_USER 3
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#define IS_EM 0
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#define IS_IA 1
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#define FPSR_VD 0
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#define FPSR_DD 1
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#define FPSR_ZD 2
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#define FPSR_OD 3
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#define FPSR_UD 4
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#define FPSR_ID 5
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#define FPSR_FTZ0 6
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#define FPSR_WRE0 7
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#define FPSR_PC0 8
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#define FPSR_RC0 10
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#define FPSR_TD0 12
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#define FPSR_V0 13
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#define FPSR_D0 14
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#define FPSR_Z0 15
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#define FPSR_O0 16
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#define FPSR_U0 17
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#define FPSR_I0 18
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#define FPSR_FTZ1 19
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#define FPSR_WRE1 20
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#define FPSR_PC1 21
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#define FPSR_RC1 23
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#define FPSR_TD1 25
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#define FPSR_V1 26
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#define FPSR_D1 27
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#define FPSR_Z1 28
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#define FPSR_O1 29
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#define FPSR_U1 30
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#define FPSR_I1 31
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#define FPSR_FTZ2 32
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#define FPSR_WRE2 33
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#define FPSR_PC2 34
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#define FPSR_RC2 36
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#define FPSR_TD2 38
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#define FPSR_V2 39
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#define FPSR_D2 40
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#define FPSR_Z2 41
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#define FPSR_O2 42
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#define FPSR_U2 43
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#define FPSR_I2 44
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#define FPSR_FTZ3 45
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#define FPSR_WRE3 46
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#define FPSR_PC3 47
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#define FPSR_RC3 49
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#define FPSR_TD3 51
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#define FPSR_V3 52
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#define FPSR_D3 53
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#define FPSR_Z3 54
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#define FPSR_O3 55
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#define FPSR_U3 56
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#define FPSR_I3 57
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#define FPSR_MBZ0 58
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#define FPSR_MBZ0_V 0x3fi64
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#define FPSR_FOR_KERNEL 0x9804C0270033F
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#define TPR_MIC 4
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#define TPR_MIC_LEN 4
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#define TPR_MMI 16
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#define TPR_IRQL_SHIFT TPR_MIC
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#define VECTOR_IRQL_SHIFT TPR_IRQL_SHIFT
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#define ISR_CODE 0
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#define ISR_CODE_LEN 16
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#define ISR_CODE_MASK 0xFFFF
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#define ISR_NA_CODE_MASK 0xF
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#define ISR_IA_VECTOR 16
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#define ISR_IA_VECTOR_LEN 8
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#define ISR_MBZ0 24
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#define ISR_MBZ0_V 0xff
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#define ISR_X 32
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#define ISR_W 33
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#define ISR_R 34
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#define ISR_NA 35
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#define ISR_SP 36
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#define ISR_RS 37
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#define ISR_IR 38
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#define ISR_NI 39
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#define ISR_MBZ1 40
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#define ISR_EI 41
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#define ISR_ED 43
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#define ISR_MBZ2 44
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#define ISR_MBZ2_V 0xfffff
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#define ISR_TPA 0
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#define ISR_FC 1
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#define ISR_PROBE 2
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#define ISR_TAK 3
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#define ISR_LFETCH 4
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#define ISR_PROBE_FAULT 5
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#define ISR_ILLEGAL_OP 0
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#define ISR_PRIV_OP 1
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#define ISR_PRIV_REG 2
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#define ISR_RESVD_REG 3
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#define ISR_ILLEGAL_ISA 4
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#define ISR_ILLEGAL_HAZARD 8
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#define ISR_NAT_REG 1
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#define ISR_NAT_PAGE 2
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#define ISR_FP_TRAP 0
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#define ISR_LP_TRAP 1
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#define ISR_TB_TRAP 2
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#define ISR_SS_TRAP 3
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#define ISR_UI_TRAP 4
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#define DCR_PP 0
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#define DCR_BE 1
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#define DCR_LC 2
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#define DCR_DM 8
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#define DCR_DP 9
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#define DCR_DK 10
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#define DCR_DX 11
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#define DCR_DR 12
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#define DCR_DA 13
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#define DCR_DD 14
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#define DCR_DEFER_ALL 0x7f00
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#define DCR_MBZ1 2
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#define DCR_MBZ1_V 0xffffffffffffi64
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#define RSC_MODE 0
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#define RSC_PL 2
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#define RSC_BE 4
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#define RSC_MBZ0 5
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#define RSC_MBZ0_V 0x3ff
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#define RSC_LOADRS 16
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#define RSC_LOADRS_LEN 14
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#define RSC_MBZ1 30
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#define RSC_MBZ1_LEN 34
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#define RSC_MBZ1_V 0x3ffffffffi64
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#define RSC_MODE_LY (0x0)
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#define RSC_MODE_SI (0x1)
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#define RSC_MODE_LI (0x2)
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#define RSC_MODE_EA (0x3)
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#define RSC_BE_LITTLE 0
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#define RSC_BE_BIG 1
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#define RSC_KERNEL ((RSC_MODE_EA<<RSC_MODE) | (RSC_BE_LITTLE<<RSC_BE))
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#define RSC_KERNEL_DISABLED ((RSC_MODE_LY<<RSC_MODE) | (RSC_BE_LITTLE<<RSC_BE))
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#define IFS_IFM 0
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#define IFS_IFM_LEN 38
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#define IFS_MBZ0 38
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#define IFS_MBZ0_V 0x1ffffffi64
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#define IFS_V 63
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#define IFS_V_LEN 1
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#define IFS_VALID 1
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#define PFS_PPL 62
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#define PFS_PPL_LEN PSR_CPL_LEN
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#define PFS_EC_SHIFT 52
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#define PFS_EC_SIZE 6
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#define PFS_EC_MASK 0x3F
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#define PFS_SIZE_SHIFT 7
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#define PFS_SIZE_MASK 0x7F
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#define NAT_BITS_PER_RNAT_REG 63
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#define RNAT_ALIGNMENT (NAT_BITS_PER_RNAT_REG << 3)
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#define RR_VE 0
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#define RR_MBZ0 1
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#define RR_PS 2
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#define RR_PS_LEN 6
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#define RR_RID 8
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#define RR_RID_LEN 24
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#define RR_MBZ1 32
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#define RR_INDEX 61
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#define RR_INDEX_LEN 3
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#define RR_PS_VE ((PAGE_SHIFT<<RR_PS) | (1<<RR_VE))
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#define NT_RR_SIZE 4
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#define RR_SIZE 8
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#define PKR_V 0
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#define PKR_WD 1
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#define PKR_RD 2
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#define PKR_XD 3
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#define PKR_MBZ0 4
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#define PKR_KEY 8
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#define PKR_KEY_LEN 24
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#define PKR_MBZ1 32
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#define PKR_VALID (1<<PKR_V)
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#define PKRNUM 16
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#define ITIR_RV0 0
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#define ITIR_PS 2
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#define ITIR_KEY 8
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#define ITIR_RV1 32
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#define IDTR_MBZ0 0
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#define IDTR_PS 2
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#define IDTR_KEY 8
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#define IDTR_MBZ1 32
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#define IDTR_IGN0 48
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#define IDTR_PPN 56
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#define IDTR_MBZ2 63
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#define IITR_MBZ0 IDTR_MBZ0
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#define IITR_PS IDTR_PS
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#define IITR_KEY IDTR_KEY
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#define IITR_MBZ1 IDTR_MBZ1
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#define IITR_IGN0 IDTR_IGN0
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#define IITR_PPN IDTR_PPN
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#define IITR_MBZ2 IDTR_MBZ2
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#define IITR_PPN_MASK 0x7FFF000000000000
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#define IITR_ATTRIBUTE_PPN_MASK 0x0003FFFFFFFFF000
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#define TR_P 0
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#define TR_RV0 1
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#define TR_MA 2
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#define TR_A 5
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#define TR_D 6
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#define TR_PL 7
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#define TR_AR 9
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#define TR_PPN 13
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#define TR_RV1 50
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#define TR_ED 52
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#define TR_IGN0 53
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#define TR_VALUE(ed,ppn,ar,pl,d,a,ma,p) ((ed << TR_ED) | (ppn & IITR_ATTRIBUTE_PPN_MASK) | (ar << TR_AR) | (pl << TR_PL) | (d << TR_D) | (a << TR_A) | (ma << TR_MA) | (p << TR_P))
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#define ITIR_VALUE(key,ps) ((ps << ITIR_PS) | (key << ITIR_KEY))
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#define PS_4K 0xC
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#define PS_8K 0xD
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#define PS_16K 0xE
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#define PS_64K 0x10
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#define PS_256K 0x12
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#define PS_1M 0x14
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#define PS_4M 0x16
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#define PS_16M 0x18
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#define PS_64M 0x1a
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#define PS_256M 0x1c
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#define NUMBER_OF_DEBUG_REGISTER_PAIRS 4
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#define DR_MASK 0
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#define DR_MASK_LEN 56
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#define DR_PLM0 56
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#define DR_PLM1 57
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#define DR_PLM2 58
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#define DR_PLM3 59
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#define DR_IG 60
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#define DR_RW 62
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#define DR_RW_LEN 2
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#define DR_X 63
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#define NUMBER_OF_PERFMON_REGISTER_PAIRS 4
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#define MASK_IA64(bp,value) (value << bp)
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#define APC_VECTOR APC_LEVEL << VECTOR_IRQL_SHIFT
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#define DISPATCH_VECTOR DISPATCH_LEVEL << VECTOR_IRQL_SHIFT
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#define OFFSET_VECTOR_BREAK 0x2800
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#define OFFSET_VECTOR_EXT_INTERRUPT 0x2c00
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#define OFFSET_VECTOR_EXC_GENERAL 0x4400
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#define PAGEMASK_4KB 0x0
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#define PAGEMASK_16KB 0x3
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#define PAGEMASK_64KB 0xf
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#define PAGEMASK_256KB 0x3f
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#define PAGEMASK_1MB 0xff
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#define PAGEMASK_4MB 0x3ff
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#define PAGEMASK_16MB 0xfff
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#define PRIMARY_CACHE_INVALID 0x0
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#define PRIMARY_CACHE_SHARED 0x1
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#define PRIMARY_CACHE_CLEAN_EXCLUSIVE 0x2
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#define PRIMARY_CACHE_DIRTY_EXCLUSIVE 0x3
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#define PS_SHIFT 2
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#define PS_LEN 6
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#define PTE_VALID_MASK 1
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#define PTE_ACCESS_MASK 0x20
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#define PTE_NOCACHE 0x10
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#define PTE_CACHE_SHIFT 2
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#define PTE_CACHE_LEN 3
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#define PTE_LARGE_PAGE 54
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#define PTE_PFN_SHIFT 8
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#define PTE_PFN_LEN 24
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#define PTE_ATTR_SHIFT 1
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#define PTE_ATTR_LEN 5
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#define PTE_PS 55
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#define PTE_OFFSET_LEN 10
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#define PDE_OFFSET_LEN 10
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#define VFN_LEN 19
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#define VFN_LEN64 24
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#define TB_USER_MASK 0x180
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#define PTE_DIRTY_MASK 0x40
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#define PTE_WRITE_MASK 0x400
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#define PTE_EXECUTE_MASK 0x200
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#define PTE_CACHE_MASK 0x0
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#define PTE_EXC_DEFER 0x10000000000000
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#define VALID_KERNEL_PTE (PTE_VALID_MASK|PTE_ACCESS_MASK|PTE_WRITE_MASK|PTE_CACHE_MASK|PTE_DIRTY_MASK)
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#define VALID_KERNEL_EXECUTE_PTE (PTE_VALID_MASK|PTE_ACCESS_MASK|PTE_EXECUTE_MASK|PTE_WRITE_MASK|PTE_CACHE_MASK|PTE_DIRTY_MASK|PTE_EXC_DEFER)
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#define PTE_VALID 0
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#define PTE_ACCESS 5
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#define PTE_OWNER 7
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#define PTE_WRITE 10
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#define PTE_LP_CACHE_SHIFT 53
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#define ATE_INDIRECT 62
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#define ATE_MASK 0xFFFFFFFFFFFFF9DE
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#define ATE_MASK0 0x621
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#define PAGE4K_SHIFT 12
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#define ALT4KB_BASE 0x6FC00000000
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#define ALT4KB_END 0x6FC00800000
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#define VRN_SHIFT 61
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#define KSEG3_VRN 4
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#define KSEG4_VRN 5
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#define MAX_PHYSICAL_SHIFT 44
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#define DISABLE_TAR_FIX 0
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#define DISABLE_BTB_FIX 1
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#define DISABLE_DATA_BP_FIX 2
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#define DISABLE_DET_STALL_FIX 3
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#define ENABLE_FULL_DISPERSAL 4
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#define ENABLE_TB_BROADCAST 5
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#define DISABLE_CPL_FIX 6
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#define ENABLE_POWER_MANAGEMENT 7
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#define DISABLE_IA32BR_FIX 8
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#define DISABLE_L1_BYPASS 9
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#define DISABLE_VHPT_WALKER 10
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#define DISABLE_IA32RSB_FIX 11
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#define DISABLE_INTERRUPTION_LOG 13
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#define DISABLE_UNSAFE_FILL 14
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#define DISABLE_STORE_UPDATE 15
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#define ENABLE_HISTORY_BUFFER 16
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#define BL_4M 0x00400000
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#define BL_16M 0x01000000
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#define BL_20M 0x01400000
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#define BL_24M 0x01800000
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#define BL_28M 0x01C00000
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#define BL_32M 0x02000000
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#define BL_36M 0x02400000
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#define BL_40M 0x02800000
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#define BL_48M 0x03000000
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#define BL_64M 0x04000000
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#define BL_80M 0x05000000
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#define BL_128M 0x08000000
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#define TR_INFO_TABLE_SIZE 10
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#define BL_SAL_INDEX 0
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#define BL_KERNEL_INDEX 1
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#define BL_DRIVER0_INDEX 2
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#define BL_DRIVER1_INDEX 3
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#define BL_DECOMPRESS_INDEX 4
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#define BL_IO_PORT_INDEX 5
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#define BL_PAL_INDEX 6
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#define BL_LOADER_INDEX 7
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#define DTR_KIPCR_INDEX 0
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#define DTR_KERNEL_INDEX 1
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#define DTR_DRIVER0_INDEX 2
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#define DTR_KTBASE_INDEX 2
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#define DTR_DRIVER1_INDEX 3
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#define DTR_UTBASE_INDEX 3
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#define DTR_VIDEO_INDEX 3
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#define DTR_KIPCR2_INDEX 4
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#define DTR_STBASE_INDEX 4
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#define DTR_IO_PORT_INDEX 5
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#define DTR_KTBASE_INDEX_TMP 6
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#define DTR_HAL_INDEX 6
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#define DTR_PAL_INDEX 6
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#define DTR_UTBASE_INDEX_TMP 7
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#define DTR_LOADER_INDEX 7
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#define DTR_UTBASE_INDEX_TMP 7
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#define ITR_EPC_INDEX 0
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#define ITR_KERNEL_INDEX 1
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#define ITR_DRIVER0_INDEX 2
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#define ITR_DRIVER1_INDEX 3
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#define ITR_HAL_INDEX 4
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#define ITR_PAL_INDEX 4
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#define ITR_LOADER_INDEX 7
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#define MEM_4K 0x1000
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#define MEM_8K 0x2000
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#define MEM_16K 0x4000
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#define MEM_64K 0x10000
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#define MEM_256K 0x40000
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#define MEM_1M 0x100000
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#define MEM_4M 0x400000
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#define MEM_16M 0x1000000
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#define MEM_64M 0x4000000
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#define MEM_256M 0x10000000
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#define MEM_SIZE_TO_PS(MemSize,TrPageSize) if (MemSize <= MEM_4K) { TrPageSize = PS_4K; } else if (MemSize <= MEM_8K) { TrPageSize = PS_8K; } else if (MemSize <= MEM_16K) { TrPageSize = PS_16K; } else if (MemSize <= MEM_64K) { TrPageSize = PS_64K; } else if (MemSize <= MEM_256K) { TrPageSize = PS_256K; } else if (MemSize <= MEM_1M) { TrPageSize = PS_1M; } else if (MemSize <= MEM_4M) { TrPageSize = PS_4M; } else if (MemSize <= MEM_16M) { TrPageSize = PS_16M; } else if (MemSize <= MEM_64M) { TrPageSize = PS_64M; } else if (MemSize <= MEM_256M) { TrPageSize = PS_256M; }
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#define NUMBER_OF_FWP_ENTRIES 8
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#define KERNEL_BASE KADDRESS_BASE+0x80000000
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#define KERNEL_BASE2 KADDRESS_BASE+0x81000000
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#define PDR_TR_INITIAL TR_VALUE(0,0,2,0,1,1,0,1)
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#define KIPCR_TR_INITIAL TR_VALUE(0,0,2,0,1,1,0,1)
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#define USPCR_TR_INITIAL TR_VALUE(0,0,0,3,1,1,0,1)
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#define PTA_INITIAL 0x001
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#define DCR_INITIAL 0x0000000000007e05
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#define PSRL_INITIAL 0x086a2008
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#define USER_PSR_INITIAL 0x00001013082a6008i64
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#define USER_FPSR_INITIAL 0x9804C0270033F
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#define USER_DCR_INITIAL 0x0000000000007f05i64
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#define USER_RSC_INITIAL ((RSC_MODE_LY<<RSC_MODE) | (RSC_BE_LITTLE<<RSC_BE) | (0x3<<RSC_PL))
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#define USER_CODE_DESCRIPTOR 0xCFBFFFFF00000000
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#define USER_DATA_DESCRIPTOR 0xCF3FFFFF00000000
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#define STACK_SCRATCH_AREA 16
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#ifdef _WIN64
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#define INT_ROUTINES_SHIFT 3
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#else
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#define INT_ROUTINES_SHIFT 2
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#endif
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#define DISABLE_INTERRUPTS(reg) mov reg = psr; rsm 1 << PSR_I
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#define RESTORE_INTERRUPTS(reg) tbit##.##nz pt0,pt1 = reg,PSR_I;; ;(pt0) ssm 1 << PSR_I ;(pt1) rsm 1 << PSR_I
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#define FAST_DISABLE_INTERRUPTS rsm 1 << PSR_I
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#define FAST_ENABLE_INTERRUPTS ssm 1 << PSR_I
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#define YIELD hint##.##m 0
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#define PCR_ENTRY 0
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#define PDR_ENTRY 2
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#define LARGE_ENTRY 3
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#define DMA_ENTRY 4
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#define TB_ENTRY_SIZE (3 *4)
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#define FIXED_BASE 0
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#define FIXED_ENTRIES (DMA_ENTRY + 1)
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#define DCACHE_SIZE 4 *1024
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#define ICACHE_SIZE 4 *1024
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#define MINIMUM_CACHE_SIZE 4 *1024
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#define MAXIMUM_CACHE_SIZE 128 *1024
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#define KSEG3_RID 0x00000
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#define START_GLOBAL_RID 0x00001
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#define HAL_RID 0x00002
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#define START_SESSION_RID 0x00003
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#define START_PROCESS_RID 0x00004
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#define MAXIMUM_RID 0x3FFFF
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#define START_SEQUENCE 1
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#define MAXIMUM_SEQUENCE 0xFFFFFFFFFFFFFFFF
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#define SBTTL(x)
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#define PROLOGUE_BEGIN .##prologue;
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#define PROLOGUE_END .##body;
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#define ALTERNATE_ENTRY(Name) .##global Name; .##type Name,@function; Name::
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#define CPUBLIC_LEAF_ENTRY(Name,i) .##text; .##proc Name##@##i; Name##@##i::
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#define LEAF_ENTRY(Name) .##text; .##global Name; .##proc Name; Name::
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#define LEAF_SETUP(i,l,o,r) .##regstk i,l,o,r; alloc r31=ar##.##pfs,i,l,o,r
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#define CPUBLIC_NESTED_ENTRY(Name,i) .##text; .##proc Name##@##i; .##unwentry; Name##@##i::
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#define NESTED_ENTRY_EX(Name,Handler) .##text; .##global Name; .##proc Name; .##personality Handler; Name::
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#define NESTED_ENTRY(Name) .##text; .##global Name; .##proc Name; Name::
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#define NESTED_SETUP(i,l,o,r) .##regstk i,l,o,r; .##prologue 0xC,loc0; alloc savedpfs=ar##.##pfs,i,l,o,r ; mov savedbrp=brp;
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#define LEAF_RETURN br##.##ret##.##sptk##.##few##.##clr brp
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#define NESTED_RETURN mov ar##.##pfs = savedpfs; mov brp = savedbrp; br##.##ret##.##sptk##.##few##.##clr brp
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#define LEAF_EXIT(Name) .##endp Name;
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#define NESTED_EXIT(Name) .##endp Name;
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#ifdef _WIN64
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#define LDPTR(rD,rPtr) ld8 rD = [rPtr]
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#else
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#define LDPTR(rD,rPtr) ld4 rD = [rPtr] ; ;; ; sxt4 rD = rD
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#endif
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#ifdef _WIN64
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#define LDPTRINC(rD,rPtr,imm) ld8 rD = [rPtr],imm
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#else
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#define LDPTRINC(rD,rPtr,imm) ld4 rD = [rPtr],imm ; ;; ; sxt4 rD = rD
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#endif
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#ifdef _WIN64
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#define PLDPTRINC(rP,rD,rPtr,imm) (rP) ld8 rD = [rPtr],imm
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#else
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#define PLDPTRINC(rP,rD,rPtr,imm) (rP) ld4 rD = [rPtr],imm ; ;; ;(rP) sxt4 rD = rD
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#endif
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#ifdef _WIN64
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#define PLDPTR(rP,rD,rPtr) (rP) ld8 rD = [rPtr]
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#else
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#define PLDPTR(rP,rD,rPtr) (rP) ld4 rD = [rPtr] ; ;; ;(rP) sxt4 rD = rD
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#endif
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#ifdef _WIN64
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#define STPTR(rPtr,rS) st8 [rPtr] = rS
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#else
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#define STPTR(rPtr,rS) st4 [rPtr] = rS
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#endif
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#ifdef _WIN64
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#define PSTPTR(rP,rPtr,rS) (rP) st8 [rPtr] = rS
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#else
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#define PSTPTR(rP,rPtr,rS) (rP) st4 [rPtr] = rS
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#endif
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#ifdef _WIN64
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#define STPTRINC(rPtr,rS,imm) st8 [rPtr] = rS,imm
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#else
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#define STPTRINC(rPtr,rS,imm) st4 [rPtr] = rS,imm
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#endif
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#ifdef _WIN64
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#define ARGPTR(rPtr)
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#else
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#define ARGPTR(rPtr) sxt4 rPtr = rPtr
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#endif
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#define ACQUIRE_SPINLOCK(rpLock,rOwn,Loop) cmp##.##eq pt0,pt1 = zero,zero ; ;; ;Loop: ;.pred.rel "mutex",pt0,pt1 ;(pt1) YIELD ;(pt0) xchg8 t22 = [rpLock],rOwn ;(pt1) ld8##.##nt1 t22 = [rpLock] ; ;; ;(pt0) cmp##.##ne pt2 = zero,t22 ; cmp##.##eq pt0,pt1 = zero,t22 ;(pt2) br##.##dpnt Loop
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#define RELEASE_SPINLOCK(rpLock) st8##.##rel [rpLock] = zero
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#define PRELEASE_SPINLOCK(px,rpLock) (px) st8##.##rel [rpLock] = zero
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#define END_OF_INTERRUPT mov cr##.##eoi = zero ; ;; ; srlz##.##d
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#ifndef SHADOW_IRQL_IMPLEMENTATION
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#define GET_IRQL(rOldIrql) mov rOldIrql = cr##.##tpr ;; extr##.##u rOldIrql = rOldIrql,TPR_MIC,TPR_MIC_LEN
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#else
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#define GET_IRQL(rOldIrql) movl rOldIrql = KiPcr+PcCurrentIrql;; ld1 rOldIrql = [rOldIrql]
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#endif
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#ifndef SHADOW_IRQL_IMPLEMENTATION
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#define SET_IRQL(rNewIrql) dep##.##z t22 = rNewIrql,TPR_MIC,TPR_MIC_LEN;; ; mov cr##.##tpr = t22;; ; srlz##.##d
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#else
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#define SET_IRQL(rNewIrql) dep##.##z t22 = rNewIrql,TPR_MIC,TPR_MIC_LEN;; ; movl t21 = KiPcr+PcCurrentIrql;; ; mov cr##.##tpr = t22 ; st1 [t21] = rNewIrql
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#endif
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#ifndef SHADOW_IRQL_IMPLEMENTATION
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#define PSET_IRQL(pr,rNewIrql) dep##.##z t22 = rNewIrql,TPR_MIC,TPR_MIC_LEN;; ;(pr) mov cr##.##tpr = t22;; ;(pr) srlz##.##d
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#else
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#define PSET_IRQL(pr,rNewIrql) mov t21 = rNewIrql ; dep##.##z t22 = rNewIrql,TPR_MIC,TPR_MIC_LEN;; ;(pr) mov cr##.##tpr = t22 ;(pr) movl t22 = KiPcr+PcCurrentIrql;; ;(pr) st1 [t22] = t21
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#endif
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#define SWAP_IRQL(rNewIrql) movl t22 = KiPcr+PcCurrentIrql;; ; ld1 v0 = [t22] ; dep##.##z t21 = rNewIrql,TPR_MIC,TPR_MIC_LEN;; ; mov cr##.##tpr = t21 ; st1 [t22] = rNewIrql
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#define GET_IRQL_FOR_VECTOR(pGet,rIrql,rVector) (pGet) shr rIrql = rVector,VECTOR_IRQL_SHIFT
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#define GET_VECTOR_FOR_IRQL(pGet,rVector,rIrql) (pGet) shl rVector = rIrql,VECTOR_IRQL_SHIFT
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#define REQUEST_APC_INT(pReq) mov t20 = 1 ; movl t21 = KiPcr+PcApcInterrupt ; ;; ;(pReq) st1 [t21] = t20
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#define REQUEST_DISPATCH_INT(pReq) mov t20 = 1 ; movl t21 = KiPcr+PcDispatchInterrupt ; ;; ;(pReq) st1 [t21] = t20
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#define beginSection(SectName) .##section .CRT$##SectName,"a","progbits"
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#define endSection(SectName)
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#define PublicFunction(Name) .##global Name; .##type Name,@function
|