302 lines
10 KiB
C
302 lines
10 KiB
C
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/*
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* ide.h
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*
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* IDE driver interface
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*
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* This file is part of the w32api package.
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*
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* Contributors:
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* Created by Herv<EFBFBD> Poussineau <hpoussin@reactos.org>
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*
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* THIS SOFTWARE IS NOT COPYRIGHTED
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*
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* This source code is offered for use in the public domain. You may
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* use, modify or distribute it freely.
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*
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* This code is distributed in the hope that it will be useful but
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* WITHOUT ANY WARRANTY. ALL WARRANTIES, EXPRESS OR IMPLIED ARE HEREBY
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* DISCLAIMED. This includes but is not limited to warranties of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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*
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*/
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#ifndef __IDE_H
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#define __IDE_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define MAX_IDE_CHANNEL 2
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#define MAX_IDE_LINE 2
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#define MAX_IDE_DEVICE 2
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#include <pshpack1.h>
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typedef struct _IDENTIFY_DATA {
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USHORT GeneralConfiguration; /* 00 */
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USHORT NumCylinders; /* 02 */
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USHORT Reserved1; /* 04 */
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USHORT NumHeads; /* 06 */
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USHORT UnformattedBytesPerTrack; /* 08 */
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USHORT UnformattedBytesPerSector; /* 10 */
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USHORT NumSectorsPerTrack; /* 12 */
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USHORT VendorUnique1[3]; /* 14 */
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UCHAR SerialNumber[20]; /* 20 */
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USHORT BufferType; /* 40 */
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USHORT BufferSectorSize; /* 42 */
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USHORT NumberOfEccBytes; /* 44 */
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UCHAR FirmwareRevision[8]; /* 46 */
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UCHAR ModelNumber[40]; /* 54 */
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UCHAR MaximumBlockTransfer; /* 94 */
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UCHAR VendorUnique2; /* 95 */
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USHORT DoubleWordIo; /* 96 */
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USHORT Capabilities; /* 98 */
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USHORT Reserved2; /* 100 */
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UCHAR VendorUnique3; /* 102 */
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UCHAR PioCycleTimingMode; /* 103 */
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UCHAR VendorUnique4; /* 104 */
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UCHAR DmaCycleTimingMode; /* 105 */
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USHORT TranslationFieldsValid:3; /* 106 */
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USHORT Reserved3:13; /* - */
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USHORT NumberOfCurrentCylinders; /* 108 */
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USHORT NumberOfCurrentHeads; /* 110 */
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USHORT CurrentSectorsPerTrack; /* 112 */
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ULONG CurrentSectorCapacity; /* 114 */
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USHORT CurrentMultiSectorSetting; /* 118 */
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ULONG UserAddressableSectors; /* 120 */
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USHORT SingleWordDMASupport:8; /* 124 */
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USHORT SingleWordDMAActive:8; /* - */
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USHORT MultiWordDMASupport:8; /* 126 */
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USHORT MultiWordDMAActive:8; /* - */
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USHORT AdvancedPIOModes:8; /* 128 */
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USHORT Reserved4:8; /* - */
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USHORT MinimumMWXferCycleTime; /* 130 */
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USHORT RecommendedMWXferCycleTime; /* 132 */
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USHORT MinimumPIOCycleTime; /* 134 */
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USHORT MinimumPIOCycleTimeIORDY; /* 136 */
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USHORT Reserved5[11]; /* 138 */
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USHORT MajorRevision; /* 160 */
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USHORT MinorRevision; /* 162 */
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USHORT Reserved6; /* 164 */
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USHORT CommandSetSupport; /* 166 */
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USHORT Reserved6a[2]; /* 168 */
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USHORT CommandSetActive; /* 172 */
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USHORT Reserved6b; /* 174 */
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USHORT UltraDMASupport:8; /* 176 */
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USHORT UltraDMAActive:8; /* - */
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USHORT Reserved7[11]; /* 178 */
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ULONG Max48BitLBA[2]; /* 200 */
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USHORT Reserved7a[22]; /* 208 */
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USHORT LastLun:3; /* 252 */
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USHORT Reserved8:13; /* - */
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USHORT MediaStatusNotification:2; /* 254 */
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USHORT Reserved9:6; /* - */
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USHORT DeviceWriteProtect:1; /* - */
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USHORT Reserved10:7; /* - */
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USHORT Reserved11[128]; /* 256 */
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} IDENTIFY_DATA, *PIDENTIFY_DATA;
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typedef struct _EXTENDED_IDENTIFY_DATA {
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USHORT GeneralConfiguration; /* 00 */
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USHORT NumCylinders; /* 02 */
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USHORT Reserved1; /* 04 */
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USHORT NumHeads; /* 06 */
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USHORT UnformattedBytesPerTrack; /* 08 */
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USHORT UnformattedBytesPerSector; /* 10 */
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USHORT NumSectorsPerTrack; /* 12 */
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union
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{
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USHORT VendorUnique1[3]; /* 14 */
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struct
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{
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UCHAR InterSectorGap; /* 14 */
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UCHAR InterSectorGapSize; /* - */
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UCHAR Reserved16; /* 16 */
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UCHAR BytesInPLO; /* - */
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USHORT VendorUniqueCnt; /* 18 */
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} u;
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};
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UCHAR SerialNumber[20]; /* 20 */
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USHORT BufferType; /* 40 */
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USHORT BufferSectorSize; /* 42 */
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USHORT NumberOfEccBytes; /* 44 */
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UCHAR FirmwareRevision[8]; /* 46 */
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UCHAR ModelNumber[40]; /* 54 */
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UCHAR MaximumBlockTransfer; /* 94 */
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UCHAR VendorUnique2; /* 95 */
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USHORT DoubleWordIo; /* 96 */
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USHORT Capabilities; /* 98 */
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USHORT Reserved2; /* 100 */
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UCHAR VendorUnique3; /* 102 */
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UCHAR PioCycleTimingMode; /* 103 */
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UCHAR VendorUnique4; /* 104 */
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UCHAR DmaCycleTimingMode; /* 105 */
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USHORT TranslationFieldsValid:3; /* 106 */
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USHORT Reserved3:13; /* - */
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USHORT NumberOfCurrentCylinders; /* 108 */
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USHORT NumberOfCurrentHeads; /* 110 */
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USHORT CurrentSectorsPerTrack; /* 112 */
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ULONG CurrentSectorCapacity; /* 114 */
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USHORT CurrentMultiSectorSetting; /* 118 */
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ULONG UserAddressableSectors; /* 120 */
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USHORT SingleWordDMASupport:8; /* 124 */
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USHORT SingleWordDMAActive:8; /* - */
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USHORT MultiWordDMASupport:8; /* 126 */
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USHORT MultiWordDMAActive:8; /* - */
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USHORT AdvancedPIOModes:8; /* 128 */
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USHORT Reserved4:8; /* - */
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USHORT MinimumMWXferCycleTime; /* 130 */
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USHORT RecommendedMWXferCycleTime; /* 132 */
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USHORT MinimumPIOCycleTime; /* 134 */
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USHORT MinimumPIOCycleTimeIORDY; /* 136 */
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USHORT Reserved5[11]; /* 138 */
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USHORT MajorRevision; /* 160 */
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USHORT MinorRevision; /* 162 */
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USHORT Reserved6; /* 164 */
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USHORT CommandSetSupport; /* 166 */
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USHORT Reserved6a[2]; /* 168 */
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USHORT CommandSetActive; /* 172 */
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USHORT Reserved6b; /* 174 */
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USHORT UltraDMASupport:8; /* 176 */
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USHORT UltraDMAActive:8; /* - */
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USHORT Reserved7[11]; /* 178 */
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ULONG Max48BitLBA[2]; /* 200 */
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USHORT Reserved7a[22]; /* 208 */
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USHORT LastLun:3; /* 252 */
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USHORT Reserved8:13; /* - */
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USHORT MediaStatusNotification:2; /* 254 */
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USHORT Reserved9:6; /* - */
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USHORT DeviceWriteProtect:1; /* - */
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USHORT Reserved10:7; /* - */
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USHORT Reserved11[128]; /* 256 */
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} EXTENDED_IDENTIFY_DATA, *PEXTENDED_IDENTIFY_DATA;
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#include <poppack.h>
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typedef struct _PCIIDE_TRANSFER_MODE_SELECT
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{
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ULONG Channel;
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BOOLEAN DevicePresent[MAX_IDE_DEVICE * MAX_IDE_LINE];
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BOOLEAN FixedDisk[MAX_IDE_DEVICE * MAX_IDE_LINE];
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BOOLEAN IoReadySupported[MAX_IDE_DEVICE * MAX_IDE_LINE];
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ULONG DeviceTransferModeSupported[MAX_IDE_DEVICE * MAX_IDE_LINE];
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ULONG BestPioCycleTime[MAX_IDE_DEVICE * MAX_IDE_LINE];
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ULONG BestSwDmaCycleTime[MAX_IDE_DEVICE * MAX_IDE_LINE];
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ULONG BestMwDmaCycleTime[MAX_IDE_DEVICE * MAX_IDE_LINE];
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ULONG BestUDmaCycleTime[MAX_IDE_DEVICE * MAX_IDE_LINE];
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ULONG DeviceTransferModeCurrent[MAX_IDE_DEVICE * MAX_IDE_LINE];
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ULONG UserChoiceTransferMode[MAX_IDE_DEVICE * MAX_IDE_LINE];
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ULONG EnableUDMA66;
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IDENTIFY_DATA IdentifyData[MAX_IDE_DEVICE];
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ULONG DeviceTransferModeSelected[MAX_IDE_DEVICE * MAX_IDE_LINE];
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PULONG TransferModeTimingTable;
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ULONG TransferModeTableLength;
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} PCIIDE_TRANSFER_MODE_SELECT, *PPCIIDE_TRANSFER_MODE_SELECT;
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typedef enum
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{
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ChannelDisabled = 0,
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ChannelEnabled,
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ChannelStateUnknown
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} IDE_CHANNEL_STATE;
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typedef IDE_CHANNEL_STATE
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(NTAPI *PCIIDE_CHANNEL_ENABLED)(
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IN PVOID DeviceExtension,
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IN ULONG Channel);
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typedef BOOLEAN
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(NTAPI *PCIIDE_SYNC_ACCESS_REQUIRED)(
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IN PVOID DeviceExtension);
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typedef NTSTATUS
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(NTAPI *PCIIDE_TRANSFER_MODE_SELECT_FUNC)(
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IN PVOID DeviceExtension,
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IN OUT PPCIIDE_TRANSFER_MODE_SELECT XferMode);
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typedef ULONG
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(NTAPI *PCIIDE_USEDMA_FUNC)(
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IN PVOID DeviceExtension,
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IN PUCHAR CdbCommand,
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IN PUCHAR Slave);
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typedef NTSTATUS
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(NTAPI *PCIIDE_UDMA_MODES_SUPPORTED)(
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IN IDENTIFY_DATA IdentifyData,
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OUT PULONG BestXferMode,
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OUT PULONG CurrentXferMode);
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typedef struct _IDE_CONTROLLER_PROPERTIES
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{
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ULONG Size;
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ULONG ExtensionSize;
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ULONG SupportedTransferMode[MAX_IDE_CHANNEL][MAX_IDE_DEVICE];
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PCIIDE_CHANNEL_ENABLED PciIdeChannelEnabled;
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PCIIDE_SYNC_ACCESS_REQUIRED PciIdeSyncAccessRequired;
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PCIIDE_TRANSFER_MODE_SELECT_FUNC PciIdeTransferModeSelect;
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BOOLEAN IgnoreActiveBitForAtaDevice;
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BOOLEAN AlwaysClearBusMasterInterrupt;
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PCIIDE_USEDMA_FUNC PciIdeUseDma;
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ULONG AlignmentRequirement;
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ULONG DefaultPIO;
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PCIIDE_UDMA_MODES_SUPPORTED PciIdeUdmaModesSupported;
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} IDE_CONTROLLER_PROPERTIES, *PIDE_CONTROLLER_PROPERTIES;
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typedef NTSTATUS
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(NTAPI *PCONTROLLER_PROPERTIES)(
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IN PVOID DeviceExtension,
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IN PIDE_CONTROLLER_PROPERTIES ControllerProperties);
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NTSTATUS NTAPI
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PciIdeXInitialize(
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IN PDRIVER_OBJECT DriverObject,
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IN PUNICODE_STRING RegistryPath,
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IN PCONTROLLER_PROPERTIES HwGetControllerProperties,
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IN ULONG ExtensionSize);
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NTSTATUS NTAPI
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PciIdeXGetBusData(
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IN PVOID DeviceExtension,
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IN PVOID Buffer,
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IN ULONG ConfigDataOffset,
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IN ULONG BufferLength);
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NTSTATUS NTAPI
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PciIdeXSetBusData(
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IN PVOID DeviceExtension,
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IN PVOID Buffer,
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IN PVOID DataMask,
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IN ULONG ConfigDataOffset,
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IN ULONG BufferLength);
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/* Bit field values for
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* PCIIDE_TRANSFER_MODE_SELECT.DeviceTransferModeSupported and
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* IDE_CONTROLLER_PROPERTIES.SupportedTransferMode
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*/
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// PIO Modes
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#define PIO_MODE0 (1 << 0)
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#define PIO_MODE1 (1 << 1)
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#define PIO_MODE2 (1 << 2)
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#define PIO_MODE3 (1 << 3)
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#define PIO_MODE4 (1 << 4)
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// Single-word DMA Modes
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#define SWDMA_MODE0 (1 << 5)
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#define SWDMA_MODE1 (1 << 6)
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#define SWDMA_MODE2 (1 << 7)
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// Multi-word DMA Modes
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#define MWDMA_MODE0 (1 << 8)
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#define MWDMA_MODE1 (1 << 9)
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#define MWDMA_MODE2 (1 << 10)
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// Ultra DMA Modes
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#define UDMA_MODE0 (1 << 11)
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#define UDMA_MODE1 (1 << 12)
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#define UDMA_MODE2 (1 << 13)
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#define UDMA_MODE3 (1 << 14)
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#define UDMA_MODE4 (1 << 15)
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#define UDMA_MODE5 (1 << 16)
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#ifdef __cplusplus
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}
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#endif
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#endif /* __IDE_H */
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